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SAN JOSE, Calif.----Nov. 6, 2000--C Level Design, Inc. today announced its membership in the Cadence Design Systems, Inc. (NYSE:CDN) Alanza(SM) Group Connections Program, a third-party software program allowing the achievement of the tightest level of interoperability between software tools. Under this program, C Level Design will offer an integrated C/C++ design flow and methodology for mutual users of Cadence® and C Level Design electronic design automation (EDA) software.

Through the Connections Program, C Level Design's C/C++ design tools, which include System Compiler® for C/C++ synthesis and CSim(TM) for C/C++ simulation, will be integrated with the Cadence HDL synthesis and simulation tools, Verilog®-XL, NC Verilog®, NC-VHDL and Ambit® BuildGates®. Together, C Level Design and Cadence tools will enable system and hardware designers to leverage the design flexibility and verification performance of C/C++ with their existing HDL design flows.

``System Compiler and our CycleC(TM) methodology are being adopted by major electronics customers who want to use our C/C++ tools within their Cadence HDL environments to raise their level of design abstraction and productivity,'' said David Park, vice president of marketing at C Level Design. ``To continue the rapid adoption of our tools and methodologies by the system and hardware community, it's critical that our tools interoperate with the HDL simulation and synthesis solutions from Cadence.''

``With C/C++ -based design gaining momentum in the marketplace, C Level Design is an important addition to our Connections Program,'' said Pat Dutrow, director of the Connections Program at Cadence. ``Now our mutual customers that choose to design with C/C++ can have a more complete design flow. By working with C Level Design, customers now have a direct path from C/C++ into our industry-leading Verilog-XL and BuildGates for HDL verification and implementation.''

About C Level Design

C Level Design, Inc. was founded in 1997 to develop and market system-level design automation software products for electrical engineers. C Level Design's tools dramatically reduce the time it takes to verify and implement complex electronic systems. The company's products enable engineers to design and verify systems at the C/C++ level for higher performance and productivity, and then automatically synthesize their designs into HDL code that is compatible with industry standard ASIC and FPGA synthesis tools. For more information, visit: http://www.cleveldesign.com

System Compiler is a registered trademark of C Level Design, CSim is a trademark of C Level Design. Cadence, the Cadence logo, Verilog-XL, NC Verilog, Ambit, and BuildGates are registered trademarks, and Alanza is a service mark of Cadence Design Systems, Inc.

     C Level Design
     David Park, 408/558-7780
     dave@cleveldesign.com
      or
     KJ Communications
     Kella Knack, 650/508-0371
     kjcomk@cs.com